AMD fires back at Nvidia, claiming 256-core Zen 6 'Venice' CPU beats Vera by 3.3x in rack-level performance — company shares first estimated EPYC Venice benchmarks

AMD Strikes Back: 256-Core Zen 6 'Venice' EPYC CPU Targets Nvidia's Vera

AMD has fired the opening salvo ahead of its upcoming Advancing AI event, releasing the first official estimated performance figures for its next-generation EPYC "Venice" processors built on the Zen 6 architecture. The company claims that a rack-scale deployment of its flagship 256-core Venice CPU delivers 3.3x the performance of Nvidia's Vera CPU within a fixed 100kW power budget — a bold statement that positions AMD firmly in the escalating server CPU arms race.

The claim represents AMD's strongest counter yet to Nvidia's aggressive push into the server CPU market with its Vera processor, which leverages the company's Grace CPU architecture and NVLink interconnect technology. However, the headline number comes with significant methodological caveats that any informed observer should consider.

Understanding the Methodology

AMD's results are based on a rack-level modeling approach rather than direct measurement of complete systems. The company estimated power based on processor TDP and additional components, then calculated how many dual-socket nodes could fit within a 100kW power budget. Performance was then extrapolated by multiplying that node count by single-node performance measured in a selection of benchmarks.

Critically, AMD does not have access to Nvidia Vera hardware. Its competitor performance estimates are derived from benchmarks AMD had for Nvidia's Grace chip, scaled by a factor of 1.63x based on Vera results published by Phoronix. Similarly, the Venice performance estimates are based on a 1.7x scaling factor over the current-generation EPYC 9965, combined with internal testing data.

AMD is transparent about these limitations. The company explicitly states that these results are "intended to provide directional comparison rather than direct measured rack benchmarks." As one analyst from Tom's Hardware noted, that sentence "carries a lot of weight on its shoulders," since you cannot simply scale single-node performance linearly — interconnects, thermal constraints, and power delivery all become significant factors at rack scale.

Benchmarks and Real-World Context

AMD frames its results around agentic AI workloads, though the primary benchmark referenced is SPEC CPU 2017, focusing specifically on integer throughput — a general-purpose data center measure rather than an AI-specific test. Additional benchmarks used in the analysis were curated by Nvidia, adding another layer of complexity to the comparison.

Community discussion around the numbers has highlighted that "all of these benchmarks and estimates are just rough notions. We'll just have to wait a few months until systems based on Vera and Venice actually get out into the wild, before we get a clear picture of how they really compare."

The comparison is further complicated by fundamental architectural differences. While AMD's Venice cores are expected to deliver strong per-core performance, Nvidia's NVLink interconnect could give Vera an advantage in tightly coupled multi-socket configurations. This means the performance story may vary significantly by workload type, with bandwidth-intensive tasks potentially favoring Vera's architecture.

Architectural Showdown: Venice vs. Vera

AMD's Zen 6 Venice architecture introduces a monumental 256-core, 512-thread configuration with up to 4TB of DRAM per CPU. By contrast, Nvidia's Vera offers 88 cores with 1.5TB of memory per chip. On a per-socket basis, Venice enjoys a significant core-count advantage. However, Nvidia can pack up to eight Vera CPUs in a single sled using its NVLink fabric, enabling up to 704 cores with 12TB of total memory in the same physical footprint where two Venice CPUs would provide 512 cores and 8TB — giving Vera a potential density advantage in memory-constrained or tightly packed deployments.

Recent engineering sample leaks have shown Zen 6 Venice chips with up to 192 cores and 32 cores per CCD in early stress testing, suggesting that AMD's validation process is well underway. The full 256-core flagship variant has not been detailed yet, but these samples provide a glimpse into the architecture's scalability.

The memory picture is similarly competitive: Venice offers approximately 8GB per thread, while Vera provides about 8.7GB per thread, placing the two architectures in a similar range for memory capacity per compute unit.

What's Next

AMD is expected to reveal full details about the Venice architecture, Zen 6 more broadly, and the complete EPYC roadmap at its Advancing AI event scheduled for next month. The event will likely include deeper dives into the architecture's AI-specific capabilities, memory subsystem details, and concrete platform specifications.

As the server CPU landscape evolves, both AMD and Nvidia are pushing the boundaries of core count, memory bandwidth, and interconnect technology. The data center market stands to benefit from this accelerated innovation cycle, with competitive pressure driving improvements in both raw performance and energy efficiency.

However, the real-world performance picture will only become clear once production hardware from both camps is independently tested in actual data center deployments — a milestone that remains several months away. Until then, AMD's estimated benchmarks offer an intriguing directional glimpse into what promises to be one of the most competitive server CPU battles in recent memory.