Google reportedly books Intel for packaging more than 3 million TPUs in 2028 — SK hynix is testing Intel's EMIB packaging for HBM integration

Intel's EMIB Packaging Wins Major Google TPU Order as TSMC's CoWoS Capacity Runs Dry

In a landmark move that reshapes the advanced semiconductor packaging landscape, Google has reportedly placed an order for Intel to package more than 3 million of its Tensor Processing Units (TPUs) in 2028, according to sources familiar with the matter. The deal comes after months of rigorous testing of Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology and signals a significant breakthrough for Intel Foundry's packaging ambitions.

The development marks a critical inflection point for Intel's foundry business, which has been working aggressively to establish itself as a credible alternative to TSMC's dominant CoWoS (Chip-on-Wafer-on-Substrate) packaging platform. With TSMC's CoWoS lines sold out through 2027, hyperscalers like Google are actively seeking second sources for advanced packaging — and Intel's EMIB has emerged as the most viable contender.

Beyond Google: Nvidia and SK hynix Join the Picture

The report, published by Tom's Hardware citing four people familiar with the matter, reveals that the implications extend far beyond Google. Nvidia is reportedly evaluating Intel to build a future processor that fuses four GPU dies into a single unit, linked to its upcoming Feynman architecture due in 2028. Meanwhile, SK hynix — the world's leading high-bandwidth memory (HBM) manufacturer — is actively testing whether its HBM stacks work reliably with Intel's EMIB packaging.

This qualification process is particularly significant. SK hynix held a 57% share of the HBM market in 2025 and reportedly secured approximately 70% of the HBM4 supply for Nvidia's Rubin platform. An official thumbs-up from SK hynix would convert Intel's packaging status from "tested" to "trusted" — a stamp of approval that could unlock billions in foundry revenue.

EMIB vs. CoWoS: Two Approaches to the Same Problem

Both EMIB and CoWoS solve the same fundamental challenge: how to interconnect multiple silicon dies — logic, memory, accelerators — in a single package with high-bandwidth, low-latency connectivity. But they take fundamentally different approaches.

TSMC's CoWoS mounts every die on a large silicon interposer that all signals and power must cross. As package sizes scale up, so does the interposer, which can drive costs significantly. Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip, compared to $900–$1,000 for CoWoS on a Rubin-class processor. Intel's approach uses small silicon bridges embedded directly into the package substrate, connecting only where needed — a more efficient use of silicon real estate.

EMIB-T: The Next Evolution

Intel's next-generation EMIB-T technology addresses one of standard EMIB's key limitations: power delivery. Standard EMIB routes power around the bridge through the substrate in long, resistive paths — acceptable for some applications but not ideal for power-hungry AI accelerators. EMIB-T closes that gap by adding through-silicon vias (TSVs) to the bridge die for vertical power delivery.

Set to enter production fab rollout this year, EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 memory stacks. It scales to a massive 120mm × 180mm package carrying more than 38 bridges and over 12 reticle-sized dies — exactly the kind of configuration that next-generation AI accelerators will demand.

Intel Foundry's High-Stakes Bet

The packaging wins couldn't come at a more critical time for Intel Foundry. The division lost $10.3 billion on $17.8 billion of revenue in 2025. In Q1 2026, it posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers accounting for just $174 million of total revenue.

However, CFO David Zinsner told the Morgan Stanley TMT conference in March that the foundry is closing deals worth "billions per year in terms of revenue" on advanced packaging alone. The Google TPU order — along with potential Nvidia and SK hynix business — would represent a dramatic acceleration of that trajectory.

The TSMC Capacity Crunch

TSMC's inability to satisfy customer demand is the key catalyst driving business toward Intel. At the company's annual shareholders' meeting in Hsinchu on June 4, CEO C.C. Wei stated plainly: "It will be a long time before we can meet customer demand." He acknowledged that TSMC falls "about three times short" of demand, even as it aggressively builds out U.S. fabrication capacity.

The CoWoS queue is concentrated among a handful of dominant buyers. Nvidia is expected to account for roughly 60% of global CoWoS demand this year, followed by Broadcom and AMD. With their primary packaging partner saturated, hyperscalers and chip designers are left with few alternatives — and Intel's EMIB is the most credible second source on the horizon.

What's at Stake

For Intel, the packaging breakthroughs represent a path to relevance in a foundry market long dominated by TSMC. Success with Google's TPU program could open the floodgates to additional hyperscaler customers. For the broader AI industry, a viable second source for advanced packaging reduces supply chain concentration risk and could help alleviate the AI chip shortage by unlocking additional packaging capacity.

Yet significant challenges remain. Intel still needs to prove EMIB at scale — no named external AI customer is in EMIB or Foveros volume production today. Process yields on Intel 18A, the company's first node with gate-all-around transistors and backside power, will be closely watched as the foundry ramps production for Panther Lake and Clearwater Forest before courting external AI chip clients.

The coming months will be decisive. An official SK hynix qualification — or better yet, an HBM4-on-EMIB-T production result — would mark the moment Intel's packaging story shifts from promise to reality. Until then, the industry watches with bated breath.